View MPC750EC_5201320.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

order number: MPC750EC/d rev. 2.3, 9/2001 semiconductor products sector this document contains information on a new product under development by motorola. motorola reserves the right to change or discontinue this product without notice. ?motorola, inc., 2001. all rights reserved. technical data mpc750a risc microprocessor hardware speci?ations this document is primarily concerned with the mpc750, however, unless otherwise noted, all information here applies also to the mpc740. the mpc750 and mpc740 are implementations of the powerpc family of reduced instruction set computing (risc) microprocessors. this document describes pertinent physical characteristics of the mpc750. for functional characteristics of the processor, refer to the mpc750 risc microprocessor users manual . the mpc750 (and mpc740) is implemented in several semiconductor fabrication processes. different processes may require different supply voltages and may have other electrical differences but will have the same functionality. as a designator to distinguish between mpc750 implementations in various processes, a suf? is added to the mpc750 part number as shown below: this document will describe only the mpc750a implementation. the xpc750p is described in a separate document. table 1. mpc750 microprocessors from motorola part number process core voltage i/o voltage 5-volt tolerant mpc750a, mpc740a 0.29 m cmos, 5lm 2.6 v 3.3 v no xpc750p, xpc740p 0.25 m cmos, 5lm 1.9 v 3.3 v no
2 mpc750a risc microprocessor hardware speci?ations this document contains the following topics: topic page section 1.1, ?verview 3 section 1.2, ?eatures 4 section 1.3, ?eneral parameters 6 section 1.4, ?lectrical and thermal characteristics 6 section 1.4.1, ?c electrical characteristics 6 section 1.4.2, ac electrical characteristics 10 section 1.4.2.1, ?lock ac speci?ations 10 section 1.4.2.2, ?0x bus input ac speci?ations 12 section 1.4.2.3, ?0x bus output ac speci?ations 14 section 1.4.2.4, ?2 clock ac speci?ations 15 section 1.4.2.5, ?2 bus input ac speci?ations 18 section 1.4.2.6, ?2 bus output ac speci?ations 19 section 1.5, ?in assignments 23 section 1.6, ?inout listings 25 section 1.7, ?ackage description 29 section 1.8, ?ystem design information 31 section 1.9, ?ocument revision history 42 to locate any published errata or updates for this document, refer to the website at http://www.mot.com/powerpc/.
mpc750a risc microprocessor hardware speci?ations 3 overview 1.1 overview the mpc750 is targeted for low-cost, low-power systems and supports the following power management features?oze, nap, sleep, and dynamic power management. the mpc750 consists of a processor core and an internal l2 tag combined with a dedicated l2 cache interface and a 60x bus. figure 1 shows a block diagram of the mpc750. figure 1. mpc750 block diagram completion instruction fetch control unit 32k icache bht/btic dispatch system unit branch unit fxu1 fxu2 gprs rename buffers lsu fpu 32k dcache l2 tags l2 cache biu fprs rename buffers 60x biu
4 mpc750a risc microprocessor hardware speci?ations features 1.2 features this section summarizes features of the mpc750s implementation of the powerpc architecture. major features of the mpc750 are as follows: branch processing unit four instructions fetched per clock one branch processed per cycle (plus resolving 2 speculations) up to 1 speculative stream in execution, 1 additional speculative stream in fetch 512-entry branch history table (bht) for dynamic prediction 64-entry, 4-way set associative branch target instruction cache (btic) for eliminating branch delay slots dispatch unit full hardware detection of dependencies (resolved in the execution units) dispatch two instructions to six independent units (system, branch, load/store, ?ed-point unit 1, ?ed-point unit 2, or ?ating-point) serialization control (predispatch, postdispatch, execution serialization) decode register ?e access forwarding control partial instruction decode load/store unit one cycle load or store cache access (byte, half-word, word, double-word) effective address generation hits under misses (one outstanding miss) single-cycle misaligned access within double word boundary alignment, zero padding, sign extend for integer register ?e floating-point internal format conversion (alignment, normalization) sequencing for load/store multiples and string operations store gathering cache and tlb instructions big- and little-endian byte addressing supported misaligned little-endian support in hardware fixed-point units fixed-point unit 1 (fxu1)?ultiply, divide, shift, rotate, arithmetic, logical fixed-point unit 2 (fxu2)?hift, rotate, arithmetic, logical single-cycle arithmetic, shift, rotate, logical multiply and divide support (multi-cycle) early out multiply floating-point unit support for ieee-754 standard single- and double-precision ?ating-point arithmetic 3 cycle latency, 1 cycle throughput, single-precision multiply-add
mpc750a risc microprocessor hardware speci?ations 5 features 3 cycle latency, 1 cycle throughput, double-precision add 4 cycle latency, 2 cycle throughput, double-precision multiply-add hardware support for divide hardware support for denormalized numbers time deterministic non-ieee mode system unit executes cr logical instructions and miscellaneous system instructions special register transfer instructions cache structure 32k, 32-byte line, 8-way set associative instruction cache 32k, 32-byte line, 8-way set associative data cache single-cycle cache access pseudo-lru replacement copy-back or write-through data cache (on a page per page basis) supports all powerpc memory coherency modes non-blocking instruction and data cache (one outstanding miss under hits) no snooping of instruction cache memory management unit 128 entry, 2-way set associative instruction tlb 128 entry, 2-way set associative data tlb hardware reload for tlbs 4 instruction bats and 4 data bats virtual memory support for up to 4 exabytes (2 52 ) of virtual memory real memory support for up to 4 gigabytes (2 32 ) of physical memory level 2 (l2) cache interface (not implemented on mpc740) internal l2 cache controller and 4k-entry tags; external data srams 256k, 512k, and 1 mbyte 2-way set associative l2 cache support copy-back or write-through data cache (on a page basis, or for all l2) 64-byte (256k/512k) and 128-byte (1-mbyte) sectored line size supports ?w-through (reg-buf) synchronous burst srams, pipelined (reg-reg) synchronous burst srams, and pipelined (reg-reg) late-write synchronous burst srams core-to-l2 frequency divisors of ?, ?.5, ?, ?.5, and ? supported bus interface compatible with 60x processor interface 32-bit address bus 64-bit data bus bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x supported integrated power management low-power 2.6/3.3-volt design three static power saving modes: doze, nap, and sleep
6 mpc750a risc microprocessor hardware speci?ations general parameters automatic dynamic power reduction when internal functional units are idle integrated thermal management assist unit on-chip thermal sensor and control logic thermal management interrupt for software regulation of junction temperature. testability lssd scan design jtag interface reliability and serviceability?arity checking on 60x and l2 cache buses 1.3 general parameters the following list provides a summary of the general parameters of the mpc750: technology: 0.29 ? cmos, ?e-layer metal die size: 7.56 mm x 8.79 mm (67 mm 2 ) transistor count 6.35 million logic design fully-static packages mpc740: surface mount 255 ceramic ball grid array (cbga) without l2 interface mpc750: surface mount 360 ceramic ball grid array (cbga) with l2 interface core power supply: 2.6v ?100 mv i/o power supply 3.3v ?5% v dc 1.4 electrical and thermal characteristics this section provides the ac and dc electrical speci?ations and thermal characteristics for the mpc750. 1.4.1 dc electrical characteristics the tables in this section describe the mpc750 dc electrical characteristics. table 2 provides the absolute maximum ratings. table 2. absolute maximum ratings characteristic symbol mpc750a value unit notes core supply voltage vdd ?0.3 to 2.75 v4 pll supply voltage avdd ?.3 to 2.75 v 4 l2 dll supply voltage l2avdd ?.3 to 2.75 v 4 60x bus supply voltage ovdd ?.3 to 3.6 v 3,5
mpc750a risc microprocessor hardware speci?ations 7 electrical and thermal characteristics figure 2 shows the allowable undershoot and overshoot voltage on the mpc750. figure 2. overshoot/undershoot voltage table 3 provides the recommended operating conditions for the mpc750. l2 bus supply voltage l2ovdd ?.3 to 3.6 v 3,5 input voltage v in ?.3 to 3.6 v 2 storage temperature range t stg ?5 to 150 ? notes : 1. functional and tested operating conditions are given in table 3. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution : v in must not exceed ovdd/l2ovdd by more than 0.3v at any time including during power-on reset. 3. caution : ovdd/l2ovdd must not exceed vdd/avdd by more than 1.2v at any time including during power-on reset. 4. caution : vdd/avdd/l2avdd must not exceed ovdd/l2ovdd by more than 0.4v at any time including during power-on reset. 5. v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 table 3. recommended operating conditions characteristic symbol mpc750a value unit notes core supply voltage vdd 2.6 100mv v pll supply voltage avdd 2.6 100mv v l2 dll supply voltage l2avdd 2.6 100mv v 60x bus supply voltage ovdd 3.135 to 3.465 v table 2. absolute maximum ratings (continued) characteristic symbol mpc750a value unit notes v ih gnd gnd - .3v gnd - 1.0v not to exceed 10% 4v v il (l2)ovdd (l2)ovdd + 5% of t sysclk
8 mpc750a risc microprocessor hardware speci?ations electrical and thermal characteristics table 4 provides the package thermal characteristics for the mpc750. the mpc750 incorporates a thermal management assist unit (tau) composed of a thermal sensor, digital-to-analog converter, comparator, control logic, and dedicated special-purpose registers (sprs). see the mpc750 risc microprocessor users manual for more information on the use of this feature. speci?ations for the thermal sensor portion of the tau are found in table 5. l2 bus supply voltage l2ovdd 2.5 to 3.465 v input voltage v in gnd to ovdd v die-junction temperature t j 0 to 105 ? t j -40 to 105 ? 1 note: these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 1. for extended temperature parts marked mpc750arxnnnth or mpc740arxnnnth only (where nnn is the operating frequency from table 8. table 4. package thermal characteristics characteristic symbol value rating cbga package thermal resistance, junction-to-case thermal resistance (typical) jc 0.03 ?/w cbga package thermal resistance, die junction-to-lead thermal resistance (typical) jb 3.8 ?/w note: refer to section 1.8, ?ystem design information, for more details about thermal management. table 5. thermal sensor specifications at recommended operating conditions (see table 3) num characteristic min max unit notes 1 temperature range 0 127 ? 1 2 comparator settling time 20 s 2 3 resolution 4 ? 3 notes: 1. the temperature is the junction temperature of the die. the thermal assist unit?s raw output does not indicate an absolute temperature, but it must be interpreted by software to derive the absolute junction temperature. for information about the use and calibration of the tau, see motorola application note an1800/d, ?programming the thermal assist unit in the mpc750 microprocessor?. 2. the comparator settling time value must be converted into the number of cpu clocks that need to be written into the thrm3 spr. 3. guaranteed by design and characterization. table 3. recommended operating conditions (continued) characteristic symbol mpc750a value unit notes
mpc750a risc microprocessor hardware speci?ations 9 electrical and thermal characteristics table 6 provides the dc electrical characteristics for the mpc750. table 7 provides the power consumption for the mpc750. table 6. dc electrical specifications at recommended operating conditions (see table 3) characteristic symbol min max unit notes input high voltage (all inputs except sysclk) v ih 1.7 l2ovdd + 0.3 v 2,3,4 v ih 2 ovdd + 0.3 v 2,3, input low voltage (all inputs except sysclk) v il -0.3 0.2 * l2ovdd v 4 v il -0.3 0.8 v sysclk input high voltage cv ih 2.4 ovdd + 0.3 v 2 sysclk input low voltage cv il -0.3 0.4 v input leakage current, v in = ovdd i in 30 a 2,3 hi-z (off-state) leakage current, v in = ovdd i tsi 30 a 2,3,6 output high voltage, i oh = -6 ma v oh 1.8 v v oh 2.4 v output low voltage, i ol = 6 ma v ol 0.4 v capacitance, v in = 0 v, f = 1 mhz c in 5.0 pf 3,5 notes: 1. nominal voltages; see table 3 for recommended operating conditions. 2. for 60x bus signals, the reference is ovdd while l2ovdd is the reference for the l2 bus signals. 3. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk) and ieee 1149.1 boundary scan (jtag) signals. 4. applicable to l2 bus interface only 5. capacitance is periodically sampled rather than 100% tested. 6. the leakage is measured for nominal ovdd and vdd, or both ovdd and vdd must vary in the same direction (for example, both ovdd and vdd vary by either +5% or -5%). table 7. power consumption for mpc750 processor (cpu) frequency unit notes 200 mhz 233 mhz 266 mhz full-on mode typical maximum 4.2 5.0 5.7 w 1, 3, 4 6.0 7.0 7.9 w 1, 2, 4 doze mode maximum 1.6 1.8 2.1 w 1, 2 nap mode maximum 250 250 250 mw 1, 2 sleep mode maximum 300 300 300 mw 1, 2
10 mpc750a risc microprocessor hardware speci?ations electrical and thermal characteristics 1.4.2 ac electrical characteristics this section provides the ac electrical characteristics for the mpc750. after fabrication, parts are sorted by maximum processor core frequency as shown in section 1.4.2.1, ?lock ac speci?ations,?and tested for conformance to the ac speci?ations for that frequency. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg[0?] signals. parts are sold by maximum processor core frequency; see section 1.10, ?rdering information? 1.4.2.1 clock ac speci?ations table 8 provides the clock ac timing speci?ations as de?ed in figure 3. sleep mode?ll and dll disabled typical 30 50 50 mw 1, 3 maximum 60 100 100 mw 1, 2 notes: 1. these values apply for all valid 60x bus and l2 bus ratios. the values do not include i/o supply power (ovdd and l2ovdd) or pll/dll supply power (avdd and l2avdd). ovdd and l2ovdd power is system dependent, but is typically <10% of vdd power. worst case power consumption for avdd = 15 mw and l2avdd = 15 mw. 2. maximum power is measured at vdd = 2.7v. 3. typical power is an average value measured at vdd = avdd = l2avdd = 2.6v, ovdd = l2ovdd = 3.3v in a system executing typical applications and benchmark sequences. 4. full-on mode is measured using worst-case instruction sequence. table 8. clock ac timing specifications at recommended operating conditions (see table 3) num characteristic 200 mhz 233 mhz 266 mhz unit notes min max min max min max processor frequency 150 200 150 233 150 266 mhz vco frequency 300 400 300 466 300 533 mhz sysclk frequency 25 83.3 25 83.3 25 83.3 mhz 1 1 sysclk cycle time 12 40 12 40 12 40 ns 2, 3 sysclk rise and fall time ? ? ? ns 2 table 7. power consumption for mpc750 (continued) processor (cpu) frequency unit notes 200 mhz 233 mhz 266 mhz
mpc750a risc microprocessor hardware speci?ations 11 electrical and thermal characteristics figure 3 provides the sysclk input timing diagram. figure 3. sysclk input timing diagram 4 sysclk duty cycle measured at 1.4v 40 60 40 60 40 60 % 3 sysclk jitter ?50 ?50 ?50 ps 4 internal pll relock time 100 100 100 s5 notes: 1. caution : the sysclk frequency and pll_cfg[0?3] settings must be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0?3] signal description in section 1.8.1, ?pll configuration,? for valid pll_cfg[0?3] settings 2. rise and fall times for the sysclk input are measured from 0.4 to 2.4v. 3. timing is guaranteed by design and characterization. 4. the total input jitter (short term and long term combined) must be under 150 ps. 5. relock timing is guaranteed by design and characterization. pll-relock time is the maximum amount of time required for pll lock after a stable vdd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. table 8. clock ac timing specifications (continued) at recommended operating conditions (see table 3) num characteristic 200 mhz 233 mhz 266 mhz unit notes min max min max min max vm vm = midpoint voltage (1.4v) 2 3 cv il cv ih 1 sysclk vm vm 4 4
12 mpc750a risc microprocessor hardware speci?ations electrical and thermal characteristics 1.4.2.2 60x bus input ac speci?ations table 9 provides the 60x bus input ac timing speci?ations for the mpc750 as de?ed in figure 4 and figure 5. input timing speci?ations for the l2 bus are provided in section 1.4.2.5, ?2 bus input ac speci?ations. table 9. 60x bus input ac timing specifications 1 at recommended operating conditions (see table 3) num characteristic 200, 233, 266 mhz unit notes min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 2.5 ns 2 10b all other inputs valid to sysclk (input setup) 3.0 ns 3 10c mode select input setup to hreset (dr tr y , tlbisync ) 8t sysclk 4,5,6,7 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 0 ns 2 11b sysclk to all other inputs invalid (input hold) 0 ns 3 11c hreset to mode select input hold (dr tr y , tlbisync ) 0 ns 4,6,7 notes: 1. all input specifications are measured from the ttl level (0.8 to 2.0v) of the signal in question to the 1.4v of the rising edge of the input sysclk. input and output timings are measured at the pin. 2. address/data/transfer attribute inputs are composed of the following?a[0?31], ap[0?3], tt[0?4], tbst , tsiz[0?2], gbl , dh[0?31], dl[0?31], dp[0?7]. 3. all other signal inputs are composed of the following?ts , abb , dbb , ar tr y , bg , aack , dbg , dbwo , t a , dr tr y , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qack , tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset (see figure 5). 5. t sysclk is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. guaranteed by design and characterization. 7. this specification is for configuration mode select only. also note that the hreset must be held asserted for a minimum of 255 bus clocks after the pll re-lock time during the power-on reset sequence.
mpc750a risc microprocessor hardware speci?ations 13 electrical and thermal characteristics figure 4 provides the input timing diagram for the mpc750. figure 4. input timing diagram figure 5 provides the mode select input timing diagram for the mpc750. figure 5. mode select input timing diagram 11a vm vm = midpoint voltage (1.4v) sysclk 11b 10a 10b all inputs v ih hreset 11c mode pins 10c v ih = 2.0v
14 mpc750a risc microprocessor hardware speci?ations electrical and thermal characteristics 1.4.2.3 60x bus output ac speci?ations table 10 provides the 60x bus output ac timing speci?ations for the mpc750 as de?ed in figure 6. output timing speci?ations for the l2 bus are provided in section 1.4.2.6, ?2 bus output ac speci?ations. table 10. 60x bus output ac timing specifications 1 at recommended operating conditions (see table 3), c l = 50 pf 2 num characteristic 200, 233, 266 mhz unit notes min max 12 sysclk to output driven (output enable time) 0.5 ns 13 sysclk to output valid (ts , abb , ar tr y , dbb ) 6.5 ns 5 14 sysclk to all other outputs valid (all except ts , abb , ar tr y , dbb ) 6.5 ns 5 15 sysclk to output invalid (output hold) 1.0 ns 3 16 sysclk to output high impedance (all except abb , ar tr y , dbb ) 6.0 ns 8 17 sysclk to abb , dbb high impedance after precharge 1.0 t sysclk 4,6,8 18 sysclk to ar tr y high impedance before precharge 5.5 ns 8 19 sysclk to ar tr y precharge enable 0.2*t sysclk +1.0 ns 3,4,7 20 maximum delay to ar tr y precharge 1 t sysclk 4,7 21 sysclk to ar tr y high impedance after precharge ?t sysclk 4,7,8 notes: 1. all output specifications are measured from the 1.4v of the rising edge of sysclk to ttl level (0.8 v or 2.0 v) of the signal in question. both input and output timing are measured at the pin. 2. all maximum timing specifications assume c l = 50 pf. 3. this minimum parameter assumes c l = 0 pf. 4. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration of the parameter in question. 5. output signal transitions from gnd to 2.0v or ovdd to 0.8v. 6. nominal precharge width for abb and dbb is 0.5 t sysclk . 7. nominal precharge width for ar tr y is 1.0 t sysclk . 8. guaranteed by design and characterization.
mpc750a risc microprocessor hardware speci?ations 15 electrical and thermal characteristics figure 6 provides the output timing diagram for the mpc750. figure 6. output timing diagram 1.4.2.4 l2 clock ac speci?ations table 11 provides the l2clk output ac timing speci?ations as de?ed in figure 7. table 11. l2clk output ac timing specifications at recommended operating conditions (see table 3) num characteristic min max unit notes l2clk frequency 80 133 mhz 1,4 22 l2clk cycle time 7.5 12.5 ns 23 l2clk duty cycle 50 % 2 sysclk 12 15 16 16 all outputs ts ar tr y abb , dbb vm vm vm = midpoint voltage (1.4v) 15 vm 18 14 13 13 17 21 19 20 (except ts , abb , ar tr y , dbb )
16 mpc750a risc microprocessor hardware speci?ations electrical and thermal characteristics internal dll-relock time 640 l2clk 3 l2clkout output-to-output skew 50 ps 5 l2clkout output jitter 150 ps 5 notes: 1. l2clk outputs are l2clk_outa, l2clk_outb and l2sync_out pins. the l2 cache interface supports higher frequencies when appropriate load conditions have been considered. the l2 i/o drivers have been designed to support a 133 mhz l2 bus loaded with 4 off-the-shelf pipelined synchronous burst srams. running the l2 bus beyond 133 mhz requires tightly coupled customized srams or a multi-chip module (mcm) implementation. the l2clk frequency to core frequency settings must be chosen such that the resulting l2clk frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. l2clk_outa and l2clk_outb must have equal loading. 2. the nominal duty cycle of the l2clk is 50% measured at midpoint voltage. 3. the dll re-lock time is specified in terms of l2clks. the number in the table must be multiplied by the period of l2clk to compute the actual time duration in nanoseconds. re-lock timing is guaranteed by design and characterization. 4. the l2cr[l2sl] bit should be set for l2clk frequencies less than 110 mhz 5. guaranteed by design and not tested. table 11. l2clk output ac timing specifications (continued) at recommended operating conditions (see table 3) num characteristic min max unit notes
mpc750a risc microprocessor hardware speci?ations 17 electrical and thermal characteristics the l2clk_out timing diagram is shown in figure 7. figure 7. l2clk_out output timing diagram vm vm = midpoint voltage (l2ovdd/2) 22 l2clk_outa vm vm 23 vm vm = midpoint voltage (l2ovdd/2) 22 l2clk_outa vm vm 23 l2clk_outb l2 differential clock mode l2 single-ended clock mode gnd l2ovdd vm l2clk_outb vm vm vm l2sync_out vm vm vm l2sync_out vm vm
18 mpc750a risc microprocessor hardware speci?ations electrical and thermal characteristics 1.4.2.5 l2 bus input ac speci?ations the l2 bus input interface ac timing speci?ations are found in table 12. figure 8 shows the l2 bus input timing diagrams for the mpc750. figure 8. l2 bus input timing diagrams table 12. l2 bus input interface ac timing specifications 1 at recommended operating conditions (see table 3) num characteristic processor frequency 200?66 mhz unit notes min max 29,30 l2sync_in rise and fall time 1.0 ns 2 24 data and parity input setup to l2sync_in 2.0 ns 25 l2sync_in to data and parity input hold 0.5 ns notes : 1. all input specifications are measured from the ttl level (0.8v or 2.0v) of the signal in question to the midpoint voltage of the rising edge of the input l2sync_in. input timings are measured at the pins (see figure 8). 2. rise and fall times for the l2sync_in input are measured from 0.4 to 2.4v. vm vm = midpoint voltage (1.4v) l2sync_in 25 24 all inputs 29 30
mpc750a risc microprocessor hardware speci?ations 19 electrical and thermal characteristics 1.4.2.6 l2 bus output ac speci?ations table 13 provides the l2 bus output interface ac timing speci?ations for the mpc750 as de?ed in figure 9. figure 9 shows the l2 bus output timing diagrams for the mpc750. table 13. l2 bus output interface ac timing specifications 1 at recommended operating conditions (see table 3), c l = 20 pf 3 num characteristic l2cr[14?5] core freq 200-266mhz min max 26 l2sync_in to output valid 00 2 5.0 01 5.5 10 5.7 11 6.0 27 l2sync_in to output hold 00 2 0.5 01 1.0 10 1.2 11 1.5 28 l2sync_in to high impedance 00 2 4.0 01 4.5 10 4.7 11 5.0 notes : 1. all outputs are measured from the midpoint voltage of the rising edge of l2sync_in to the ttl level (0.8v or 2.0v) of the signal in question. the output timings are measured at the pins. 2.the outputs are valid for both single-ended and differential l2clk modes. for flow-thru and pipelined reg-reg synchronous burst rams, l2cr[14?15] = 00 is recommended. for pipelined delay-write synchronous burst srams, l2cr[14?15] = 01 is recommended. 3. all maximum timing specifications assume c l =20 pf. 4. this measurement assumes c l = 5 pf.
20 mpc750a risc microprocessor hardware speci?ations electrical and thermal characteristics figure 9. l2 bus output timing diagrams 1.4.3 ieee 1149.1 ac timing speci?ations table 14 provides the ieee 1149.1 (jtag) ac timing speci?ations as de?ed in figure 10, figure 11, figure 12, and figure 13. table 14. jtag ac timing specifications (independent of sysclk) at recommended operating conditions (see table 3), c l = 50 pf num characteristic min max unit notes tck frequency of operation 0 33.3 mhz 1 tck cycle time 30 ns 2 tck clock pulse width measured at 1.4v 15 ns 3 tck rise and fall times 0 2 ns 4 speci?ation obsolete, intentionally omitted 5 trst assert time 25 ns 1 6 boundary-scan input data setup time 4 ns 2 7 boundary-scan input data hold time 15 ns 2 8 tck to output data valid 4 20 ns 3 9 tck to output high impedance 3 19 ns 3, 4 10 tms, tdi data setup time 0 ns 27 vm vm = midpoint voltage (1.4v) l2sync_in 26 all outputs vm 28 l2data bus
mpc750a risc microprocessor hardware speci?ations 21 electrical and thermal characteristics figure 10 provides the jtag clock input timing diagram. figure 10. jtag clock input timing diagram figure 11 provides the trst timing diagram. figure 11. trst timing diagram 11 tms, tdi data hold time 12 ns 12 tck to tdo data valid 4 12 ns 13 tck to tdo high impedance 3 9 ns 4 notes: 1. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 2. non-jtag signal input timing with respect to tck. 3. non-jtag signal output timing with respect to tck. 4. guaranteed by design and characterization. table 14. jtag ac timing specifications (independent of sysclk) (continued) at recommended operating conditions (see table 3), c l = 50 pf num characteristic min max unit notes tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage 5 trst
22 mpc750a risc microprocessor hardware speci?ations electrical and thermal characteristics figure 12 provides the boundary-scan timing diagram. figure 12. boundary-scan timing diagram figure 13 provides the test access port timing diagram. figure 13. test access port timing diagram 6 7 input data valid 8 9 8 output data valid output data valid tck data inputs data outputs data outputs data outputs 10 11 input data valid 12 13 12 output data valid output data valid tck tdi, tms tdo tdo tdo
mpc750a risc microprocessor hardware speci?ations 23 pin assignments 1.5 pin assignments figure 14 (in part a) shows the pinout of the mpc740, 255 cbga package as viewed from the top surface. part b shows the side pro?e of the cbga package to indicate the direction of the top surface view. part a figure 14. pinout of the mpc740, 255 cbga package as viewed from the top surface a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 not to scale view part b die substrate assembly encapsulant
24 mpc750a risc microprocessor hardware speci?ations pin assignments figure 15 (in part a) shows the pinout of the mpc750, 360 cbga package as viewed from the top surface. part b shows the side pro?e of the cbga package to indicate the direction of the top surface view. part a figure 15. pinout of the mpc750, 360 cbga package as viewed from the top surface a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 not to scale 17 18 19 u v w view part b die substrate assembly encapsulant
mpc750a risc microprocessor hardware speci?ations 25 pinout listings 1.6 pinout listings table 15 provides the pinout listing for the mpc740, 255 cbga package. table 15. pinout listing for the mpc740, 255 cbga package signal name pin number active i/o a[0?1] c16, e4, d13, f2, d14, g1, d15, e2, d16, d4, e13, g2, e15, h1, e16, h2, f13, j1, f14, j2, f15, h3, f16, f4, g13, k1, g15, k2, h16, m1, j15, p1 high i/o aa ck l2 low input abb k4 low i/o ap[0?] c1, b4, b3, b2 high i/o artry j4 low i/o a vdd a10 bg l1 low input br b6 low output ci e1 low output ckstp_in d8 low input ckstp_out a6 low output clk_out d7 output dbb j14 low i/o dbg n1 low input dbdis h15 low input dbw o g4 low input dh[0?1] p14, t16, r15, t15, r13, r12, p11, n11, r11, t12, t11, r10, p9, n9, t10, r9, t9, p8, n8, r8, t8, n7, r7, t7, p6, n6, r6, t6, r5, n5, t5, t4 high i/o dl[0?1] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n12, t13, p3, n3, n4, r3, t1, t2, p4, t3, r4 high i/o dp[0?] m2, l3, n2, l4, r1, p2, m4, r2 high i/o dr tr y g16 low input gbl f1 low i/o gnd c5, c12, e3, e6, e8, e9, e11, e14, f5, f7, f10, f12, g6, g8, g9, g11, h5, h7, h10, h12, j5, j7, j10, j12, k6, k8, k9, k11, l5, l7, l10, l12, m3, m6, m8, m9, m11, m14, p5, p12 hreset a7 low input int b15 low input l1_tstclk 1 d11 high input l2_tstclk 1 d12 high input lssd_mode 1 b10 low input mcp c13 low input nc (no?onnect) b7, b8, c3, c6, c8, d5, d6, h4, j16, a4, a5, a2, a3, b1, b5 ovdd c7, e5, e7, e10, e12, g3, g5, g12, g14, k3, k5, k12, k14, m5, m7, m10, m12, p7, p10 pll_cfg[0?] a8, b9, a9, d9 high input
26 mpc750a risc microprocessor hardware speci?ations pinout listings table 16 provides the pinout listing for the mpc750, 360 cbga package. qa ck d3 low input qreq j3 low output rsr v d1 low output smi a16 low input sreset b14 low input sysclk c9 input t a h14 low input tben c2 high input tbst a14 low i/o tck c11 high input tdi a11 high input tdo a12 high output tea h13 low input tlbisync c4 low input tms b11 high input trst c10 low input ts j13 low i/o tsiz[0?] a13, d10, b12 high output tt[0?] b13, a15, b16, c14, c15 high i/o wt d2 low output vdd 2 f6, f8, f9, f11, g7, g10, h6, h8, h9, h11, j6, j8, j9, j11, k7, k10, l6, l8, l9, l11 voltdet 3 f3 high output notes: 1. these are test signals for factory use only and must be pulled up to ovdd for normal machine operation. 2. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. 3. internally tied to gnd in the mpc740 cbga package to indicate to the power supply that a low-voltage processor is present. this signal is not a power supply input. table 16. pinout listing for the mpc750, 360 cbga package signal name pin number active i/o a[0?1] a13, d2, h11, c1, b13, f2, c13, e5, d13, g7, f12, g3, g6, h2, e2, l3, g5, l4, g4, j4, h7, e1, g2, f3, j7, m3, h3, j2, j6, k3, k2, l2 high i/o aa ck n3 low input abb l7 low i/o ap[0?] c4, c5, c6, c7 high i/o ar tr y l6 low i/o avdd a8 bg h1 low input table 15. pinout listing for the mpc740, 255 cbga package (continued) signal name pin number active i/o
mpc750a risc microprocessor hardware speci?ations 27 pinout listings br e7 low output ckstp_out d7 low output ci c2 low output ckstp_in b8 low input clkout e3 output dbb k5 low i/o dbdis g1 low input dbg k1 low input dbw o d1 low input dh[0?1] w12, w11, v11, t9, w10, u9, u10, m11, m9, p8, w7, p9, w9, r10, w6, v7, v6, u8, v9, t7, u7, r7, u6, w5, u5, w4, p7, v5, v4, w3, u4, r5 high i/o dl[0?1] m6, p3, n4, n5, r3, m7, t2, n6, u2, n7, p11, v13, u12, p12, t13, w13, u13, v10, w8, t11, u11, v12, v8, t1, p1, v1, u1, n1, r2, v3, u3, w2 high i/o dp[0?] l1, p2, m2, v2, m1, n2, t3, r1 high i/o dr tr y h6 low input gbl b1 low i/o gnd d10, d14, d16, d4, d6, e12, e8, f4, f6, f10, f14, f16, g9, g11, h5, h8, h10, h12, h15, j9, j11, k4, k6, k8, k10, k12, k14, k16, l9, l11, m5, m8, m10, m12, m15, n9, n11, p4, p6, p10, p14, p16, r8, r12, t4, t6, t10, t14, t16 hreset b6 low input int c11 low input l1_tstclk 1 f8 high input l2addr[0?6] l17, l18, l19, m19, k18, k17, k15, j19, j18, j17, j16, h18, h17, j14, j13, h19, g18 high output l2avdd l13 l2ce p17 low output l2clk out a n15 low output l2clk outb l16 low output l2data[0?3] u14, r13, w14, w15, v15, u15, w16, v16, w17, v17, u17, w18, v18, u18, v19, u19, t18, t17, r19, r18, r17, r15, p19, p18, p13, n14, n13, n19, n17, m17, m13, m18, h13, g19, g16, g15, g14, g13, f19, f18, f13, e19, e18, e17, e15, d19, d18, d17, c18, c17, b19, b18, b17, a18, a17, a16, b16, c16, a14, a15, c15, b14, c14, e13 high i/o l2dp[0?] v14, u16, t19, n18, h14, f17, c19, b15 high i/o l2ovdd d15, e14, e16, h16, j15, l15, m16, p15, r14, r16, t15, f15 l2sync_in l14 input l2sync_out m14 output l2_tstclk 1 f7 high input table 16. pinout listing for the mpc750, 360 cbga package (continued) signal name pin number active i/o
28 mpc750a risc microprocessor hardware speci?ations pinout listings l2we n16 low output l2zz g17 high output lssd_mode 1 f9 low input mcp b11 low input nc (no?onnect) b3, b4, b5, a19, w19, w1, k9, k11 4 , k19 4 ovdd d5, d8, d12, e4, e6, e9, e11, f5, h4, j5, l5, m4, p5, r4, r6, r9, r11, t5, t8, t12 pll_cfg[0?] a4, a5, a6, a7 high input qa ck b2 low input qreq j3 low output rsr v d3 low output smi a12 low input sreset e10 low input sysclk h9 input t a f1 low input tben a2 high input tbst a11 low i/o tck b10 high input tdi b7 high input tdo d9 high output tea j1 low input tlbisync a3 low input tms c8 high input trst a10 low input ts k7 low i/o tsiz[0?] a9, b9, c9 high output tt[0?] c10, d11, b12, c12, f11 high i/o wt c3 low output vdd 2 g8, g10, g12, j8, j10, j12, l8, l10, l12, n8, n10, n12 voltdet 3 k13 high output notes: 1. these are test signals for factory use only and must be pulled up to ovdd for normal machine operation. 2. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. 3. internally tied to l2ovdd in the mpc750 cbga package to indicate the power present at the l2 cache interface. this signal is not a power supply input. caution : this is different from the mpc740 cbga package. 4. these pins are reserved for potential future use as additional l2 address pins. table 16. pinout listing for the mpc750, 360 cbga package (continued) signal name pin number active i/o
mpc750a risc microprocessor hardware speci?ations 29 package description 1.7 package description the following sections provide the package parameters and mechanical dimensions for the mpc740, 255 cbga packages. 1.7.1 parameters for the mpc740 the package parameters are as provided in the following list. the package type is 21 x 21 mm, 255-lead ceramic ball grid array (cbga). package outline 21 x 21 mm interconnects 255 (16 x 16 ball array - 1) pitch 1.27 mm (50 mil) minimum module height 2.45 mm maximum module height 3.00 mm ball diameter 0.89 mm (35 mil) 1.7.2 mechanical dimensions of the mpc740 figure 16 provides the mechanical dimensions and bottom surface nomenclature of the mpc740, 255 cbga package.
30 mpc750a risc microprocessor hardware speci?ations package description figure 16. mechanical dimensions and bottom surface nomenclature of the mpc740 1.7.3 parameters for the mpc750 the package parameters are as provided in the following list. the package type is 25 x 25 mm, 360-lead ceramic ball grid array (cbga). package outline 25 x 25 mm interconnects 360 (19 x 19 ball array - 1) pitch 1.27 mm (50 mil) minimum module height 2.65 mm maximum module height 3.20 mm ball diameter 0.89 mm (35 mil) notes: dimensioning and tolerancing per asme y14.5m, 1994. dimensions in millimeters. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball 0.2 b c 255x d 2x a1 corner e e e1 d1 0.2 2x b a 12345678910111213141516 a b c d e f g h j k l m n p r t e/2 a 0.3 c 0.15 b e/2 a a1 a2 c 0.15 c m millimeters dim min max a 2.45 3.00 a1 0.79 0.99 a2 0.9 1.10 b 0.82 0.93 d 21.00 bsc d1 8.3 8.5 e 1.27 bsc e 21.00 bsc e1 9.0 9.2 m 2.00
mpc750a risc microprocessor hardware speci?ations 31 system design information 1.7.4 mechanical dimensions of the mpc750 figure 17 provides the mechanical dimensions and bottom surface nomenclature of the mpc750, 360 cbga package. figure 17. mechanical dimensions and bottom surface nomenclature of the mpc750 1.8 system design information this section provides electrical and thermal design recommendations for successful application of the mpc750. dim min max millimeters a 2.72 3.20 a1 0.80 1.00 a2 1.10 1.30 a3 --- 0.60 a4 0.82 0.90 b d 25.00 bsc d1 22.86 bsc d2 --- 12.50 d3 2.75 --- d4 6.00 9.00 e 1.27 bsc e 25.00 bsc e1 22.86 bsc e2 --- 14.30 e3 3.00 --- e4 8.00 11.00 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is the maximum solder ball diameter measured parallel to datum a. 4. d2 and e2 define the area occupied by the die and underfill. actual size of this area may be smaller than shown. d3 and e3 are the minimum clearance from the package edge to the chip capacitors. 5. capacitors may not be present on all devices. 6. caution must be taken not to short exposed metal capacitor pads on package top. 0.3 a 0.15 a 0.25 a c l a d e c e4 e2 b 1 pin a1 index 2x d4 d2 d3 2x e3 top view 18x 2x 0.2 0.2 2x 0.35 a 0.15 a b c 0.82 0.93 bottom view w v u t r p n m l k j h g f e d c b a 12345678910111213141516171819 c l side view a d1 e1 360x b e 18x e a1 a2 a3 a4 360x
32 mpc750a risc microprocessor hardware speci?ations system design information 1.8.1 pll con?uration the mpc750s pll is con?ured by the pll_cfg[0?] signals. for a given sysclk (bus) frequency, the pll con?uration signals set the internal cpu and vco frequency of operation. the pll con?uration for the mpc750 is shown in table 17 for nominal frequencies. table 17. mpc750 microprocessor pll configuration pll_cfg [0?] sample bus-to-core frequency in mhz (vco frequency in mhz) bus-to- core multiplier core-to vco multiplier bus 25 mhz bus 33.3 mhz bus 40 mhz bus 50 mhz bus 66.6 mhz bus 75 mhz bus 83.3 mhz 1000 3x 2x 150 (300) 200 (400) 225 (450) 250 (500) 1110 3.5x 2x 175 (350) 233 (466) 262 (525) 1010 4x 2x 160 (320) 200 (400) 266 (533) 0111 4.5x 2x 150 (300) 180 (360) 225 (450) 1011 5x 2x 166 (333) 200 (400) 250 (500) 1001 5.5x 2x 183 (366) 220 (440) 1101 6x 2x 150 (300) 200 (400) 240 (480) 0101 6.5x 2x 162 (325) 216 (433) 260 (520) 0010 7x 2x 175 (350) 233 (466) 0001 7.5x 2x 187 (375) 250 (500) 1100 8x 2x 200 (400) 266 (533) 0011 pll off/bypass pll off, sysclk clocks core circuitry directly, 1x bus-to-core implied 1111 pll off pll off, no core clocking occurs notes: 1. pll_cfg[0?3] settings not listed are reserved. 2. the sample bus-to-core frequencies shown are for reference only. some pll configurations may select bus, core, or vco frequencies which are not useful, not supported, or not tested for by the mpc750; see section 1.4.2.1, ?clock ac specifications,? for valid sysclk and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note : the ac timing specifications given in this document do not apply in pll-bypass mode. 4. in clock-off mode, no clocking occurs inside the mpc750 regardless of the sysclk input.
mpc750a risc microprocessor hardware speci?ations 33 system design information table 18 provides sample core-to-l2 frequencies. 1.8.2 pll power supply filtering the avdd and l2avdd power signals are provided on the mpc750 to provide power to the clock generation phase-locked loop and l2 cache delay-locked loop respectively. to ensure stability of the internal clock, the power supplied to the avdd input signal should be ?tered using a circuit similar to the one shown in figure 18. the circuit should be placed as close as possible to the avdd pin to ensure it ?ters out as much noise as possible. an identical but separate circuit should be placed as close as possible to the l2avdd pin. figure 18. pll power supply filter circuit 1.8.3 decoupling recommendations due to the mpc750s dynamic power management feature, large address and data buses, and high operating frequencies, the mpc750 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc750 system, and the mpc750 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each vdd and ovdd pin (and l2ovdd for the 360 cbga) of the mpc750. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, and gnd power planes in the pcb, utilizing short traces to minimize inductance. table 18. sample core-to-l2 frequencies core frequency in mhz ? ?.5 ? ?.5 ? 200 200 133.3 100 80 208.3 208 138.6 104 83.3 210 210 140 105 84 220 220 146.6 110 88 225 225 150 112.5 90 233.3 233.3 155.5 116.6 93.3 240 240 160 120 96 80 266 266 177.3 133 106.4 88.6 note: the core and l2 frequencies are for reference only. some con?urations may select core or l2 frequencies which are not useful, not supported, or not tested for by the mpc750; see section 1.4.2.4, ?2 clock ac speci?ations, for valid l2clk frequencies. the l2cr[l2sl] bit should be set for l2clk frequencies less than 110 mhz. vdd avdd (or l2avdd) 10 ? 10 ? 0 . 1 ? gnd
34 mpc750a risc microprocessor hardware speci?ations system design information these capacitors should vary in value from 220 pf to 10 f to provide both high- and low-frequency ?tering, and should be placed as close as possible to their associated vdd or ovdd pins. suggested values for the vdd pins?20 pf (ceramic), 0.01 ? (ceramic), and 0.1 ? (ceramic). suggested values for the ovdd pins?.01 ? (ceramic), 0.1 ? (ceramic), and 10 ? (tantalum). only smt (surface mount technology) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd and ovdd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?00 ? (avx tps tantalum) or 330 ? (avx tps tantalum). 1.8.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to vdd. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external vdd, ovdd, and gnd pins of the mpc750. external clock routing should ensure that the rising-edge of the l2 clock is coincident at the clk input of all srams and at the l2sync_in input of the mpc750. the l2clkouta network could be used only, or the l2clkoutb network could also be used depending on the loading, frequency, and number of srams. 1.8.5 output buffer dc impedance the mpc750 60x and l2 i/o drivers were characterized over process, voltage, and temperature. to measure z 0 , an external resistor is connected to the chip pad, either to ovdd or ognd. then, the value of such resistor is varied until the pad voltage is ovdd/2; see figure 19. the output impedance is actually the average of two components, the resistances of the pull-up and pull-down devices. when data is held low, sw1 is closed (sw2 is open), and r n is trimmed until pad = ovdd/2. r n then becomes the resistance of the pull-down devices. when data is held high, sw2 is closed (sw1 is open), and r p is trimmed until pad = ovdd/2. r p then becomes the resistance of the pull-up devices. with a properly designed driver r p and r n are close to each other in value. then z 0 = (r p + r n )/2.
mpc750a risc microprocessor hardware speci?ations 35 system design information figure 19. driver impedance measurement table 19 summarizes the signal impedance results. the driver impedance values were derived by simulation at 65 ?. as the process varies, the output impedance will be reduced by several ohms. table 19. impedance characteristics vdd = 2.6v, ovdd = 3.3v, tj = 65 c process 60x l2 symbol unit typ 43 38 z 0 ohms ovdd ognd r n r p pad data sw1 sw2
36 mpc750a risc microprocessor hardware speci?ations system design information 1.8.6 pull-up resistor requirements the mpc750 requires high-resistive (weak: 10 k ? ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the mpc750 or other bus masters. these signals are ts , abb , dbb , and ar tr y . in addition, the mpc750 has one open-drain style output that requires a pull-up resistors (weak or stronger: 4.7 k ? ?0 k ? ) if it is used by the system. this signal is ckstp_out . during inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may ?at in the high-impedance state for relatively long periods of time. since the mpc750 must continually monitor these signals for snooping, this ?at condition may cause excessive power draw by the input receivers on the mpc750 or by other receivers in the system. it is recommended that these signals be pulled up through weak (10 k ? ) pull-up resistors or restored in some manner by the system. the snooped address and transfer attribute inputs are a[0?1], ap[0?], tt[0?], tbst , and gbl . the data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. other data bus receivers in the system, however, may require pullups, or that those signals be otherwise driven by the system during inactive periods. the data bus signals are dh[0?1], dl[0?1], dp[0?]. if address or data parity is not used by the system, and the respective parity checking is disabled through hid0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. if all parity generation is disabled through hid0, then all parity checking should also be disabled through hid0, and all parity pins may be left unconnected by the system. no pull-up resistors are normally required for the l2 interface. 1.8.7 thermal management information this section provides thermal management information for the ceramic ball grid array (cbga) package for air-cooled applications. proper thermal control design is primarily dependent upon the system-level design?he heat sink, air?w and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods?dhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see figure 20. this spring force should not exceed 5.5 pounds of force.
mpc750a risc microprocessor hardware speci?ations 37 system design information figure 20. package exploded cross-sectional view with several heat sink options the board designer can choose between several types of heat sinks to place on the mpc750. there are several commercially-available heat sinks for the mpc750 provided by the following vendors: chip coolers inc. 800-227-0254 (usa/canada) 333 strawberry field rd. 401-739-7600 warwick, ri 02887-6979 international electronic research corporation (ierc) 818-842-7277 135 w. magnolia blvd. burbank, ca 91502 thermalloy 214-243-4321 2021 w. valley view lane p.o. box 810839 dallas, tx 75731 wake?ld engineering 617-245-5900 60 audubon rd. wake?ld, ma 01880 aavid engineering 603-528-3400 one kool path laconia, nh 03247-0440 ultimately, the ?al selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. adhesive or thermal interface material heat sink cbga package heat sink clip printed-circuit board option
38 mpc750a risc microprocessor hardware speci?ations system design information 1.8.7.1 internal package conduction resistance for the exposed-die packaging technology, shown in table 4, the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case (or top-of-die for exposed silicon) thermal resistance the die junction-to-ball thermal resistance figure 21 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. figure 21. c4 package with heat sink mounted to a printed-circuit board heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and ?ally to the heat sink where it is removed by forced-air convection. since the silicon thermal resistance is quite small, for a ?st-order analysis, the temperature drop in the silicon may be neglected. thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. 1.8.7.2 adhesives and thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 22 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, ?roether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease signi?antly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 20). this spring force should not exceed 5.5 pounds of force. therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. of course, the selection of any thermal interface material depends on many factors?hermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. external resistance external resistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package
mpc750a risc microprocessor hardware speci?ations 39 system design information figure 22. thermal performance of select thermal interface material the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: dow-corning corporation 517-496-4000 dow-corning electronic materials po box 0997 midland, mi 48686-0997 chomerics, inc. 617-935-4850 77 dragon court woburn, ma 01888-4850 thermagon inc. 216-741-7659 3256 west 25th street cleveland, oh 44109-1668 loctite corporation 860-571-5100 1001 trout brook crossing rocky hill, ct 06067 ai technology (e.g. eg7655) 609-882-2332 1425 lower ferry rd. trent, nj 08618 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease contact pressure (psi) specific thermal resistance (kin 2 /w)
40 mpc750a risc microprocessor hardware speci?ations system design information the following section provides a heat sink selection example using one of the commercially available heat sinks. 1.8.7.3 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( jc + int + sa ) * p d where : t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation the die-junction temperatures (t j ) should be maintained less than the value speci?d in table 3. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 ?. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 ?. the thermal resistance of the thermal interface material ( int ) is typically about 1 ?/w. assuming a t a of 30 ?, a t r of 5 ?, a cqfp package jc = 2.2, and a power consumption (p d ) of 4.5 watts, the following expression for t j is obtained: die-junction temperature: t j = 30 ? + 5 ? + (2.2 ?/w + 1.0 ?/w + sa ) * 4.5 w for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance ( sa ) versus air?w velocity is shown in figure 23.
mpc750a risc microprocessor hardware speci?ations 41 system design information figure 23. thermalloy #2328b heat sink-to-ambient thermal resistance versus airflow velocity assuming an air velocity of 0.5 m/s, we have an effective r sa of 7 ?/w, thus t j = 30 ? + 5 ? + (2.2 ?/w +1.0 ?/w + 7 ?/w) * 4.5 w, resulting in a die-junction temperature of approximately 81 ? which is well within the maximum operating temperature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, wake?ld engineering, and aavid engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air ?w. though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common ?ure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat ?w. the ?al die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the ?al operating die-junction temperature?ir?w, board population (local heat ?x of adjacent components), heat sink ef?iency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. to expedite system-level thermal analysis, several ?ompact?thermal-package models are available within flotherm? these are available upon request. 1 3 5 7 8 0 0.5 1 1.5 2 2.5 3 3.5 thermalloy #2328b pin-fin heat sink approach air velocity (m/s) heat sink thermal resistance (?/w) (25 x28 x 15 mm) 2 4 6
42 mpc750a risc microprocessor hardware speci?ations document revision history 1.9 document revision history 1.10 ordering information this section provides the part numbering nomenclature for the mpc750. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local motorola sales of?e. figure 24 provides the motorola part numbering nomenclature for the mpc750. in addition to the processor frequency, the part numbering scheme also consists of a part modi?r and application modi?r. the part modi?r indicates any enhancement(s) in the part from the original production design. the bus divider may specify special bus frequencies or application conditions. each part number also contains a table 20. document revision history document revision substantive change(s) rev 1 modi?d introduction to indicate this document also addresses mpc750p parts fabricated in .19? process with attendant changes in supply voltages and electrical characteristics. changed section 1.3, ?eneral parameters, to include new technology, die size, and core power supply for mpc750p. changed table 2 to include absolute maximum supply voltage for mpc750p. changed table 3 to include recommended supply voltages for mpc750p and extended l2 bus supply voltage down to 2.5v for all parts. added table 7 to provide power consumption of mpc750p. changed table 8, table 9, and table 10 to show test conditions appropriate to the process and add 300 mhz to ac speci?ations. changed table 9 to reduce input hold time (spec 11a and 11b) from 1ns to 0ns for all cpu frequencies. changed table 11, table 12 and table 13 to show extended test conditions for l2ovdd and add 300mhz to ac speci?ations. changed table 13 and table 14 to show test conditions appropriate to the process. rev 2 removed preliminary overlay from document deleted electrical speci?ations for the mpc750p part and created a separate speci?ation describing the unique operating conditions of that part. corrected active polarity of ckstp_out , ckstp_in , l2ce , l2we , l2sync_in, l2sync_out in table 17. added extended junction temperature parts to table 3. rev 2.1 removed 333mhz column from table 13. rev 2.2 in table 7, maximum sleep power is increased to 300 mw. rev 2.3 corrected figure 16 and figure 17, which omitted some dimensions due to format error.
mpc750a risc microprocessor hardware speci?ations 43 ordering information revision code. this refers to the die mask revision number and is speci?d in the part numbering scheme for identi?ation purposes only. figure 24. motorola part number key mpc 750 a rx xxx x x product code part identifier part modifier package (rx = bga) processor frequency (contact local motorola sales office) revision level application modifier (l = any valid pll configuration (740 or 750) t=extended temperature)
information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. ther e are no express or implied copyright licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual perfor mance may vary over time. all operating parameters, including ?ypicals?must be validated for each customer application by customer? technical ex perts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or autho rized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, o r for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer pu rchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employe es, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that moto rola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu. minato-ku, tokyo 106-8573 japan. 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong . 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments : fax (512) 933-2625, attn: risc applications engineering world wide web addresses : http://www.motorola.com/powerpc http://www.motorola.com/netcomm MPC750EC/d digitaldna is a trademark of motorola, inc. the powerpc name, the powerpc logotype, and powerpc 603e are trademarks of international business machines corporation used by motorola under license from international business machines corporation.

▲Up To Search▲

Price & Availability of MPC750EC

	To Download MPC750EC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .